The present invention relates generally to the field of integrated circuit manufacturing, and more specifically, to depositing and removing sacrificial material from voids or openings in a dielectric layer on a semiconductor substrate.
Sacrificial material has been used in integrated circuit manufacturing to fill voids or openings in a dielectric layer on a semiconductor substrate. Sacrificial material generally has been a spin-on-polymer (SOP) or spin-on-glass (SOG) that is deposited by spin coating to completely fill openings in the dielectric layer. For example, sacrificial material has been used in processes for providing dual damascene metal interconnects in integrated circuits.
The dual damascene concept involves forming both a via and a trench in the dielectric layer or interlayer dielectric (ILD). For example, the via may be etched first. After sacrificial material is deposited to fill the via and leave between about 500 and 3,000 angstroms of the material on the surface of the device, the trench is etched. The use of sacrificial material allows the trench lithography and etching process to effectively apply to a substantially hole-free surface, similar to a surface without vias. Sacrificial material may be selected so that when the trench is etched, the sacrificial material may be removed at a faster rate than the dielectric layer.
After etching the trench, any remaining sacrificial material may be cleaned out and removed from the via by a combination of plasma processing and wet chemistry steps. Depending on the type of sacrificial material used, various wet etch chemistries may be used to remove the remaining sacrificial material, including buffered oxide etch processes or chemistry based on commercially available amine based materials. After the remaining sacrificial material is removed, the via and trench may be filled with a conductive material such as copper to form a complete conductive layer of interconnects. Chemical metal polishing (CMP) then may be performed to remove excess material and planarize the surface.
Although the various chemical etch steps for dissolution of the sacrificial material may have high selectivity for sacrificial material over dielectric material, they nevertheless can damage or remove dielectric materials used for the ILD. Dielectric materials with lower dielectric constants (K) are needed to reduce capacitive coupling and cross talk between adjacent metal lines in dual damascene structures. However, as the ILD dielectric constant is reduced, ILD resistance to damage during cleaning and removal of sacrificial material also is reduced. Thus, for dual damascene interconnects to realize their full potential, especially in sub 0.25 micron process technology, the problem of damage to the dielectric layer during removal and cleaning of sacrificial material must be addressed.
Thus, there is a need for sacrificial material that can be used to fill voids or openings in a dielectric layer and can be removed or cleaned out without also damaging or removing the dielectric. There is a need to reduce defects and improve yield by enabling a more efficient and effective cleaning procedure to remove sacrificial material in ILD materials and especially ILD materials with low dielectric constants. There is a need for dual damascene process that enables use of ILD materials having lower dielectric constants.